This invention relates to a semiconductor memory device and a manufacturing method thereof and more particularly to a semiconductor memory device including memory cell units (NAND cells, AND cells, DINOR cells and the like) each constructed by connecting a plurality of memory cells having conductive bodies of booster plates and a method for manufacturing the same.
Conventionally, an electrically rewritable EEPROM is known as one of the semiconductor memory devices. Among them, a NAND type EEPROM having NAND strings each constructed by serially connecting a plurality of memory cells receives much attention because it can be formed with high integration density.
The NAND type EEPROM is disclosed in K. -D. Suh et al., "A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," IEEE J. Solid-State Circuits, vol. 30, pp. 1149-1156, November 1995 (document 1) and Y. Iwata et al., "A 35 ns Cycle Time 3.3V Only 32 Mb NAND Flash EEPROM," IEEE J. Solid-State Circuits, vol. 30, pp. 1157-1164, November 1995 (document 2).
In the program operation of the EEPROM disclosed in the above documents, the channel potential of a program inhibition NAND string in the selected block is determined by the capacitive coupling between the word line and the channel. Therefore, in order to set the program inhibition voltage to a sufficiently high voltage, it is important to sufficiently effect the initial charging operation of the channel and set the capacitive coupling ratio between the word Line and the channel to a relatively large value.
The capacitive coupling ratio B between the word line and the channel is calculated by the following equation. EQU B=Cox/(Cox+Cj)
where Cox is the total sum of the gate capacitances between the word line and the channel and Cj is the total sum of junction capacitances of the source and drain of a cell transistor.
On page 1153 of the document 1, it is described that the coupling ratio is 80%, but in order to obtain this value, it is necessary to reduce the junction capacitance Cj to 1/4 of that of the conventional case, for example. However, in order to reduce the junction capacitance, the impurity concentration of a P well must be made low or the impurity concentrations of the source and drain of the cell transistor must be made low. If the impurity concentration of the P well is lowered, the field withstand voltage between memory cells will be lowered, and therefore, there is a limitation in lowering the impurity concentration. Further, if the impurity concentrations of the source and drain of the cell transistor are lowered, the resistances of the source and drain are increased, thereby causing a cell current to be reduced.
Therefore, as a method for increasing the gate capacitance Cox and reducing the junction capacitance Cj, there is proposed a method for setting the word line pitch to 2F when the design rule is set to F, and as a result, reducing the space between the adjacent word lines to reduce the junction capacitance Cj as is disclosed in a document by R. Shirota et al., "A 2.3 .mu.m.sup.2 Memory Cell Structure for 16 Mb NAND EEPROMs," in IEDM'90 Technical Digest, pp. 103-106, December 1990 (document 3).
However, in this method, since two mask members are used when the word line is etched, there occurs a problem that misalignment occurs between a silicon nitride film (SiN) which is the first mask member and a resist which is the second mask member. Therefore, a problem relating to the process occurs and the manufacturing yield is lowered. Further, two processing masks for word lines are required and the manufacturing process becomes complicated and the manufacturing cost is made high.
Further, a method for reducing the junction capacitance Cj by negatively biasing the P well at the time of program to expand the depletion layer of the junction capacitance is provided. However, the junction capacitance is approximately inversely proportional to the reciprocal of the square root of the sum of the built-in potential of the junction and the reverse bias. Therefore, even if -2V is applied to the P well with respect to the channel potential of 6V, for example, the junction capacitance is reduced to only approx. 90% and a significant effect cannot be expected. Further, an additional circuit, power and time for applying a negative bias to the P well are required.
As described above, various methods for increasing the coupling ratio B are proposed, but each method has the problem as described above.
In the document 2 and Tanaka et al., "A Quick Intelligent Program Architecture for 3V-Only NAND-EEPROM's," in Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp. 20-21 (document 4), the channel potential of the program inhibition NAND string at the time of program is applied in a manner different from that of the document 1. That is, in the document 1, the channel potential is raised by use of the capacitive coupling between the word line and the channel set in the electrically floating state, but in the document 2 and document 4, a program inhibition voltage raised by the charge pump of the peripheral circuit in the chip is directly applied to the channel from the sense amplifier via the bit line.
As the problem of the EEPROM described in the document 2 and document 4, the following two problems are given. First, since the program inhibition voltage is supplied from the sense amplifier to the bit line, it is necessary to form the transistors constituting the sense amplifier by use of high breakdown voltage transistors on the design condition of the sense amplifier.
When the power supply voltage vcc is 3.3V, a transistor applied with the voltage Vcc can be designed as a transistor which has a thin gate oxide film having a film thickness of 120 angstrom, for example, and has a short gate length. That is, the transistor can be designed by use of the severe design rule of 0.4 .mu.m, for example.
However, if the program inhibition voltage is set at 8V, it is required to design a transistor which can withstand the voltage as a transistor having a thick gate oxide film with a film thickness of 200 angstrom, for example, and has a long gate length of 1 .mu.m. That is, it is necessary to design the transistor with the relatively large design rule of 1 .mu.m, for example. Therefore, the layout area of the sense amplifier is increased and it is difficult to arrange the sense amplifier in the narrow bit line pitch.
As the second problem, it becomes necessary to apply a high voltage to a selected gate line and non-selected word line which correspond to pass transistors by taking the threshold voltages thereof into consideration in order to input the program inhibition voltage to the channel via the bit line. Application of a high voltage to the non-selected word line causes a problem that the non-selected cell of the NAND string to be programmed is erroneously programmed. Therefore, in the document 2 and document 4, the program inhibition voltage is limited to such a potential which does not cause the erroneous programning and there occurs a problem that the permissible potential width (window) of the program inhibition voltage is narrowed.
Further, if a high voltage is applied to the selected gate line, a strong electric field is applied to the gate oxide film of the NAND string to be programmed since the channel potential of the NAND string to be programmed is Vss (0V), and there occurs a problem that the gate oxide film of the selected gate transistor will be broken.
As the measure for coping with the above problems, recently, a NAND type EEPROM in which the channel potential of a non-programming NAND string is set high by use of conductive bodies of booster plates and the program/erase/read voltage is lowered is proposed. The NAND type EEPROM having the booster plates is disclosed in a document by J. D. Choi et al., "A Novel Booster Plate Technology in High Density NAND Flash Memories for Voltage Scaling-Down and Zero Program Disturbance," in Symp. VLSI Technology Dig. Tech. Papers, June 1996, pp. 238-239 (document 5).
The NAND type EEPROM having the booster plates has two advantages. The first advantage is that the capacitive coupling .gamma. at the time of program becomes large. In the NAND type EEPROM having no booster plate, the capacitive coupling .gamma. is expressed by the following equation. EQU .gamma.=Ccf/(Cfs+Ccf)
where Ccf is a capacitance between the control gate (word line) and the floating gate and Cfs is a capacitance between the floating gate and the substrate. The capacitive coupling .gamma.b of the NAND type EEPROM having the booster plates is expressed by the following equation. EQU .gamma.b=(Ccf+Cbf)/(Cfs+Ccf+Cbf)
where Cbf is a capacitance between the booster plate and the floating gate. Thus, the capacitive coupling .gamma.b is larger than the capacitive coupling .gamma. in a case where no booster plate is used. Therefore, the program voltage at the time of program can be lowered.
Since the capacitive coupling ratio at the time of erase is expressed by (1-.gamma.b), the potential difference between the substrate and the floating gate can be made large and it is possible to attain a high speed erase operation or lower the erase voltage in comparison with a case where no booster plate is used. Further, if .gamma.b is increased, a voltage applied to the pass transistor at the read time can be lowered.
The second advantage is that the capacitive coupling ratio between the control gate (word line) and the channel becomes larger. The capacitive coupling ratio Bb in a case where the booster plates are used is expressed by the following equation. EQU Bb=(Cox+Cboot)/(Cox+Cboot+Cj)
where Cox is the total sum of gate capacitances between the control gate (word line) and the channel, Cboot is the total sum of gate capacitances between the booster plate and the channel and Cj is the total sum of junction capacitances of the source and drain of the cell transistor. Therefore, even if the voltage of the pass transistor is not excessively raised at the time of program, the channel potential of the program inhibition NAND string can be raised and the margin against the erroneous programming can be increased.
In the NAND type EEPROM described in the document 5, the capacitance Cbf between the booster plate and the floating gate is determined by the area of the side wall of the floating gate. Therefore, in order to further increase the capacitance Cbf, it is necessary to increase the film thickness of the floating gate to make the side wall high, reduce the film thickness of the plate oxide film lying between the side wall of the floating gate and the booster plate, or increase the dielectric constant of a material of the plale oxide film.
However, if the film thickness of the floating gate is increased, a difference in level in the floating gate becomes larger, making it difficult to effect the succeeding process. Further, if the film thickness of the plate oxide film is reduced or a material with the high dielectric constant is used as the plate oxide film, there is a limitation in the reliability. Therefore, in the NAND type EEPROM described in the document 5, it is difficult to further increase the capacitance Cbf and lower the program, erase, read voltages.
Further, in the NAND type EEPROM described in the document 5, since the ion-implantation into the source/drain regions of the cell transistors of the NAND string is effected after the control gates (word lines) are formed, there occurs a problem that the coupling ratio between the control gate (word line) and the channel is made smaller by the junction capacitance Cj.